The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2007
Filed:
Nov. 26, 2001
Matthew D. Ornes, Madison, WI (US);
Christopher I. W. Norrie, San Jose, CA (US);
Gene K. Chui, Campbell, CA (US);
Onchuen (Daryn) Lau, Saratoga, CA (US);
Matthew D. Ornes, Madison, WI (US);
Christopher I. W. Norrie, San Jose, CA (US);
Gene K. Chui, Campbell, CA (US);
Onchuen (Daryn) Lau, Saratoga, CA (US);
Integrated Device Technology, Inc., San Jose, CA (US);
Abstract
A programmably sliceable switch-fabric unit (PSSU) and methods of use are disclosed. An N×N' switch matrix is programmably made to operate as if it were a plurality of S×S′ virtual switch slices, where S<N and S′<N′. Ingressing requests each specify an egress path (unicast mode) or plural egress paths (multicast mode) in terms of one or more relative egress port numbers. A request translator converts relative egress port numbers into absolute egress port numbers by determining what virtual slice each request belongs to. The translated egress requests are handed off to an arbitration and/or scheduling mechanism for further processing. If the translated request is granted, the corresponding payload egresses through the actual egress port(s) which the translated request asked for. An inventory of PSSU's may be distributed in accordance with the disclosure to segmented markets such that each PSSU can service the specific needs of a market, be it providing a plurality of 4×4 switch slices, 8×8 switch slices, 16×16 switch slices, or otherwise. In one embodiment, virtual slices are distributed throughout a physical switch-matrix so as to minimize pinout crossover for external line card units.