The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2007
Filed:
Apr. 30, 2003
David Modrie, Leuven, BE;
Koen Vanhoof, Leuven, BE;
Aalbert Stek, Eindhoven, NL;
Koninklijke Philips Electronics N. V., Eindhoven, NL;
Abstract
A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means () for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means () for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter () converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator () for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means () for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector () for deriving the data sequence (ak) from the equivalent processed sequence (ye),whereby the ratio between the sample rates 1/T and 1/Ts is substantially constant. Conventional synchronous receivers which comprise a Sample Rate Converter have the disadvantage that the digital processing is performed within the control loop of the SRC. The delay resulting from the digital processing contributes to the overall delay of the loop, which can lead to instabilities, especially when high bandwidths are require. Therefore the receiver of the invention does the digital processing outside the control loop. To keep the advantage that the digital processing can be done at a fixed rate, the converting means () are controlled by a preset value for keeping the ratio T/Ts constant.