The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2007

Filed:

Dec. 08, 2003
Applicants:

Jurriaan Schmitz, Hengelo, NL;

Raymond J. E. Hueting, Helmond, NL;

Erwin A. Hijzen, Blanden, BE;

Andreas H. Montree, Valkenswaard, NL;

Michael A. A. In't Zandt, Veldhoven, NL;

Gerrit E. J. Koops, Kessel-Lo, BE;

Inventors:

Jurriaan Schmitz, Hengelo, NL;

Raymond J. E. Hueting, Helmond, NL;

Erwin A. Hijzen, Blanden, BE;

Andreas H. Montree, Valkenswaard, NL;

Michael A. A. In't Zandt, Veldhoven, NL;

Gerrit E. J. Koops, Kessel-Lo, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A vertical insulated gate transistor is manufactured by providing a trench () extending through a source layer () and a channel layer () towards a drain layer (). A spacer etch is used to form gate portions () along the trench side walls, a dielectric material () is filled into the trench between the sidewalls gate portions (), and a gate electrical connection layer () is formed at the top of the trench electrically connecting the gate portions () across the trench.


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