The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2007

Filed:

Aug. 17, 2005
Applicants:

Raymond Albert Fillion, Niskayuna, NY (US);

Richard Alfred Beaupre, Pittsfield, MA (US);

Ahmed Elasser, Latham, NY (US);

Robert John Wojnarowski, Ballston Lake, NY (US);

Charles Steven Korman, Schenectady, NY (US);

Inventors:

Raymond Albert Fillion, Niskayuna, NY (US);

Richard Alfred Beaupre, Pittsfield, MA (US);

Ahmed Elasser, Latham, NY (US);

Robert John Wojnarowski, Ballston Lake, NY (US);

Charles Steven Korman, Schenectady, NY (US);

Assignee:

General Electric Company, Niskayuna, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/111 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip packaging structure comprising a dielectric film having one or more through holes aligned with the one or more contact pads of at least one power semiconductor chip. A patterned electrically conductive layer adjacent to the dielectric film has one or more electrically conductive posts which extend through the one or more though holes aligned with the contact pads to electrically couple the conductive layer to the contact pads. In certain embodiments, one or more air gaps may be formed between the dielectric film and the active surface of the at least one power semiconductor chip. Methods for fabricating the semiconductor chip packaging structure are also disclosed.


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