The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7262065 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 28, 2007

Filed:

Sep. 14, 2005
Applicants:

Hiroyuki Mitsui, Mie, JP;

Katsuo Takano, Nagano, JP;

Shinichi Fukada, Tokyo, JP;

Hiroshi Matsuki, Nagano, JP;

Inventors:

Hiroyuki Mitsui, Mie, JP;

Katsuo Takano, Nagano, JP;

Shinichi Fukada, Tokyo, JP;

Hiroshi Matsuki, Nagano, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.


Find Patent Forward Citations

Mitsui, Hiroyuki. (2007). Ferroelectric memory and its manufacturing method (U.S. Patent No. 7262065). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7262065

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