The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2007
Filed:
Dec. 15, 2003
Barthelemy Fondeur, Mountain View, CA (US);
Anca L. Sala, Sunnyvale, CA (US);
Robert J. Brainard, Sunnyvale, CA (US);
David K. Nakamoto, San Jose, CA (US);
Tom Truong, San Jose, CA (US);
Sanjay M. Thekdi, Santa Clara, CA (US);
Anantharaman Vaidyanathan, San Jose, CA (US);
Barthelemy Fondeur, Mountain View, CA (US);
Anca L. Sala, Sunnyvale, CA (US);
Robert J. Brainard, Sunnyvale, CA (US);
David K. Nakamoto, San Jose, CA (US);
Tom Truong, San Jose, CA (US);
Sanjay M. Thekdi, Santa Clara, CA (US);
Anantharaman Vaidyanathan, San Jose, CA (US);
JDS Uniphase Corporation, Milpitas, CA (US);
Abstract
The present application relates to a method of fabricating planar circuits using a photo lithographic mask set, to the photo lithographic mask set, and to a planar circuit fabricated with the photo lithographic mask set. The instant invention involves separating a photo lithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photo lithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.