Initializing function block registers using value supplying setting interface coupled to table linking block identifier to multiple register address set

Abstract

A processor () having an instruction memory () supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (), and address values of the registers are outputted from an address output unit () based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.