The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2007
Filed:
Sep. 30, 2004
Applicants:
Yasuhisa Takeyama, Yokohama, JP;
Osamu Hirabayashi, Tokyo, JP;
Inventors:
Yasuhisa Takeyama, Yokohama, JP;
Osamu Hirabayashi, Tokyo, JP;
Assignee:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A semiconductor device having hierarchized bit lines including an upper-layer bit line and a lower-layer bit line, includes at least one memory cell array to which the lower-layer bit line is connected and a selection transfer gate having an NMOS switching transistor and a PMOS switching transistor to connect the lower-layer bit line to the upper-layer bit line. The NMOS switching transistor and the PMOS switching transistor of the selection transfer gate are arranged opposite to each other in a column direction to sandwich the memory cell array.