The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2007

Filed:

Feb. 17, 2006
Applicants:

Naoya Sato, Sakata, JP;

Akihito Narita, Sakata, JP;

Satoru Akatsuka, Sakata, JP;

Tsutomu Abe, Tsuruoka, JP;

Inventors:

Naoya Sato, Sakata, JP;

Akihito Narita, Sakata, JP;

Satoru Akatsuka, Sakata, JP;

Tsutomu Abe, Tsuruoka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/02 (2006.01); H01B 13/00 (2006.01); H01R 13/648 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a wiring board, including: providing a resin substrate on which is formed a metal layer including a first layer and a second layer formed on the first layer; forming an interconnecting pattern by etching the metal layer so that the interconnecting pattern includes the patterned first layer and second layer and a part of the first layer remains outside the second layer as a residue of the first layer; electroless plating the interconnecting pattern and the residue of the first layer; and then washing the resin substrate. The washing of the resin substrate is performed by using at least one of an acidic solution used for dissolving and removing the residue of the first layer and a metal deposited on the residue of the first layer by the electroless plating and an alkaline solution used for dissolving the resin substrate to remove an area which supports the residue of the first layer.


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