The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2007

Filed:

Oct. 13, 2004
Applicants:

Ali H. Burney, Fremont, CA (US);

Sanjay Charagulla, San Jose, CA (US);

Daniel Mansur, Emerald Hills, CA (US);

Inventors:

Ali H. Burney, Fremont, CA (US);

Sanjay Charagulla, San Jose, CA (US);

Daniel Mansur, Emerald Hills, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/42 (2006.01); G06F 12/00 (2006.01); H04K 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus provide PCI Express support on a programmable device. A device includes a hard-coded transceiver that supports functionality associated with the PCI Express physical layer and link layer. The hard-coded transceiver can also support part of the PCI Express transaction layer. Soft-coded logic is used to support higher layer functionality including a portion of the transaction layer to allow custom configuration of PCI Express features such as virtual channels, buffers, prioritization, and quality of service characteristics. The hybrid solution reduces logic resource cost and provides an effective custom configurable solution.


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