The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2007

Filed:

Dec. 12, 2000
Applicants:

Frank H. Levinson, Palo Alto, CA (US);

Gerald F. Sage, Chico, CA (US);

Arthur Michael Lawson, Morgan Hill, CA (US);

Willem A. Mostert, Issaquah, WA (US);

Inventors:

Frank H. Levinson, Palo Alto, CA (US);

Gerald F. Sage, Chico, CA (US);

Arthur Michael Lawson, Morgan Hill, CA (US);

Willem A. Mostert, Issaquah, WA (US);

Assignee:

Finisar Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 10/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

An optical signal return path system includes a transmitter having a sample clock generator for generating a sample clock and an RF signal receiver for receiving and converting an analog RF data signal into a first data stream of digitized RF data samples at a rate determined by the sample clock. Supplemental channel circuitry provides a second data stream. A multiplexor receives and combines the first data stream and second data stream, and an optical transmitter converting the combined data stream into a serialized optical data signal for transmission over an optical fiber. The second data stream may contain maintenance data reflecting an operational state of the transmitter. A receiver receives the optical data signal and recovers therefrom a digital data stream and an associated first clock having an associated first clock rate. The data stream is stored in a memory device at the first clock rate. A clock generator generates a second clock having an associated second clock rate that is adjusted in accordance with a clock control signal. A control circuit reads data from the memory device at a rate corresponding to the second clock rate and generates a fullness signal that indicates whether the memory device is more full than a predefined threshold fullness level. A clock speed adjusting circuit generates the clock control signal in accordance with the fullness signal.


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