The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2007
Filed:
Nov. 30, 2004
Craig T. Salling, Cupertino, CA (US);
Charvaka Duvvury, Plano, TX (US);
Gianluca Boselli, Richardson, TX (US);
Craig T. Salling, Cupertino, CA (US);
Charvaka Duvvury, Plano, TX (US);
Gianluca Boselli, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A protection circuit for protecting an integrated circuit padagainst an ESD pulse, which comprises a discharge circuit having an elongated MOS transistor(preferably pMOS) in a substrate(preferably n-type), said discharge circuit operable to discharge the ESD pulse to the pad, to ground. The embodiment further contains a pump circuit connected to the pad for receiving a portion of the pulse's current; the pump circuit comprises a componentdetermining the size of this current portion (for example, another transistor, a string of forward diodes, or a reverse Zener diode), wherein the component is connected to ground. A discrete resistor(for example about 40 to 60Ω) is connected between the pad and the component and is operable to generate a voltage drop (about 0.5 to 1.0 V) by the current portion. A plurality of contacts to the substrate connects to the resistor so that the voltage drop is uniformly impressed on the substrate to ensure uniform turn-on of the elongated transistor for uniform pulse discharge.