The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 07, 2007

Filed:

May. 04, 2004
Applicants:

Wayson J. Lowe, Belmont, CA (US);

Eunice Y. D. Hao, Saratoga, CA (US);

Tony K. Ngai, Saratoga, CA (US);

Peter H. Alfke, Los Altos Hills, CA (US);

Inventors:

Wayson J. Lowe, Belmont, CA (US);

Eunice Y. D. Hao, Saratoga, CA (US);

Tony K. Ngai, Saratoga, CA (US);

Peter H. Alfke, Los Altos Hills, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first-in, first-out ('FIFO') memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.


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