Delay line based multiple frequency generator circuits for cdma processing

Abstract

A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line () having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of F. A second delay line () also receives the reference clock at an input. A logic circuit () combines signals from the delay line taps of the first delay line () with signals from the delay line taps of the second and/or first delay line () to produce a collection of clock pulses having a combined clock rate of F*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register () contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.