The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2007
Filed:
Sep. 26, 2002
Peter D. Brewer, Westlake Village, CA (US);
Michael G. Case, Thousand Oaks, CA (US);
Andrew T. Hunter, Woodland Hills, CA (US);
Mehran Matloubian, Encino, CA (US);
John A. Roth, Ventura, CA (US);
Carl W. Pobanz, Rancho Palos Verdes, CA (US);
Peter D. Brewer, Westlake Village, CA (US);
Michael G. Case, Thousand Oaks, CA (US);
Andrew T. Hunter, Woodland Hills, CA (US);
Mehran Matloubian, Encino, CA (US);
John A. Roth, Ventura, CA (US);
Carl W. Pobanz, Rancho Palos Verdes, CA (US);
HRL Laboratories, LLC, Malibu, CA (US);
Abstract
A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.