The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 07, 2007
Filed:
Sep. 14, 2004
Daniel Charles Kerr, Orlando, FL (US);
Roscoe T. Luce, Kissimmee, FL (US);
Michele Marie Jamison, Sanford, FL (US);
Alan Sangone Chen, Windermere, FL (US);
William A. Russell, Orlando, FL (US);
Daniel Charles Kerr, Orlando, FL (US);
Roscoe T. Luce, Kissimmee, FL (US);
Michele Marie Jamison, Sanford, FL (US);
Alan Sangone Chen, Windermere, FL (US);
William A. Russell, Orlando, FL (US);
Agere Systems, Inc., Allentown, PA (US);
Abstract
A semiconductor manufacturing method comprises forming a leveling guard ring defining an interior area into which are fabricated one or more devices. In certain aspects, two or more matched devices, such as in a common centroid layout, are fabricated in the interior area. The guard ring is formed on at least one particular layer for a particular processing step. By the guard ring overwhelming the effect of local features' elevation differences, photoresist thereafter applied consequently has a more uniform height across the interior area, resulting in more uniform devices. A plurality of guard rings may be used that enclose respective arrays of matched devices arranged over the surface of a semiconductor wafer. Based on the equalizing effect by each of the guard rings, the respective devices arranged in the interior areas are more evenly matched to equivalent devices in far-spaced guard rings. Thus, local and global matching are achieved.