The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7251761 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 31, 2007

Filed:

Aug. 11, 2003
Applicants:

Wataru Itoh, Kyoto, JP;

Tomohiko Kanemitsu, Osaka, JP;

Takeru Yamashita, Osaka, JP;

Akihiko Watanabe, Osaka, JP;

Inventors:

Wataru Itoh, Kyoto, JP;

Tomohiko Kanemitsu, Osaka, JP;

Takeru Yamashita, Osaka, JP;

Akihiko Watanabe, Osaka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

An assembly for an LSI test supplies a test signal output from an LSI tester to a target LSI to be tested and outputs, to the LSI tester, a test result signal generated by processing of the target LSI performed in accordance with the test signal. The assembly for an LSI test includes: a peripheral circuit coupled to the target LSI and allowing the target LSI to operate in the same manner as in the application environment; and a printed circuit board on which the peripheral circuit is mounted.


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Itoh, Wataru. (2007). Assembly for lsi test and method for the test (U.S. Patent No. 7251761). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7251761

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