The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2007
Filed:
Jul. 15, 2005
Lawrence C. Gunn, Iii, Encinitas, CA (US);
Thierry J. Pinguet, Cardiff-By-The-Sea, CA (US);
Maxime Jean Rattier, Paris, FR;
Lawrence C. Gunn, III, Encinitas, CA (US);
Thierry J. Pinguet, Cardiff-By-The-Sea, CA (US);
Maxime Jean Rattier, Paris, FR;
Luxtera, Inc., Carlsbad, CA (US);
Abstract
In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.