The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2007

Filed:

Jun. 07, 2005
Applicants:

Subramani Kengeri, San Jose, CA (US);

Deepak Sabharwal, New Delhi, IN;

Prakash Bhatia, Fremont, CA (US);

Shreekanth Sampigethaya, San Jose, CA (US);

Sanjiv Kainth, New Delhi, IN;

Inventors:

Subramani Kengeri, San Jose, CA (US);

Deepak Sabharwal, New Delhi, IN;

Prakash Bhatia, Fremont, CA (US);

Shreekanth Sampigethaya, San Jose, CA (US);

Sanjiv Kainth, New Delhi, IN;

Assignee:

Virage Logic Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.


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