The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2007
Filed:
Jul. 14, 2004
Cheng-hsiung Huang, Cupertino, CA (US);
Chih-ching Shih, Pleasanton, CA (US);
Jeffrey Tyhach, Sunnyvale, CA (US);
Guu Lin, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Stephanie T. Tran, San Jose, CA (US);
Cheng-Hsiung Huang, Cupertino, CA (US);
Chih-Ching Shih, Pleasanton, CA (US);
Jeffrey Tyhach, Sunnyvale, CA (US);
Guu Lin, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Stephanie T. Tran, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Circuits are described that provide electrostatic discharge protection for I/O circuits that support the low voltage differential signaling (LVDS) and on-chip termination (OCT) standards. At least one additional transistor is connected across an I/O transistor. In the case of LVDS, a pair of stacked transistors is used in which the distance between the source/drain region and a well tap is considerably greater for the transistor connected to the I/O pad. A PMOS transistor and an NMOS transistor may also be connected in series between a first node such as a power supply node and the I/O pad. An OCT circuit is also disclosed in which the spacing between the source/drain region and a well tap in the OCT transistor is smaller than that in the I/O transistor.