The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2007
Filed:
Aug. 06, 2004
Curtis Hall, Denison, TX (US);
Curtis Hall, Denison, TX (US);
GlobiTech Incorporated, Sherman, TX (US);
Abstract
The present invention is directed to a wafer device method for processing same. A wafer for epitaxial deposition is backside sealed with a dopant seal layer (protection layer comprised of silicon dioxide or silicon nitride. Then, a layer of polysilicon is formed coextensively over the dopant seal layer. The polysilicon layer acts as a seed layer for potentially nodule forming gasses present during epitaxial deposition. During CVD epitaxy, the epitaxial layer is deposited on the primary surface with optimal resistivity uniformity. The fugitive gasses from the epitaxial process which diffuse to the wafer periphery and backside deposit as a film on the seed layer instead of in nodules. The polysilicon layer acts as a continuous seed layer which eliminates the preferential deposition at seal layer pinholes or island seed sites. The resulting structure of silicon substrate, dopant seal layer, polysilicon seed layer provides for nodule-free epitaxial deposition without increasing auto-doping and escalating the epitaxial resistivity non-uniformities. Alternatively, the wafer is sealed on the backside and peripheral edges with a dopant seal layer. Then, a layer of polysilicon is formed over the entire extent of the dopant seal layer. CVD epitaxy is performed, growing an epitaxial layer on the front side and depositing a film layer on the back side and peripheral edges of the wafer. The fugitive gasses from the epitaxial process which diffuse to the wafer backside and edge deposit as a film on the seed layer instead of in nodules. The amount of out-gassing is reduced because the peripheral edges of the wafer are covered with the dopant seal layer and since that layer is not exposed to the reaction gases, silicon spur and nodule formation is thwarted.