The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2007
Filed:
Jun. 30, 2003
Francis G. Celii, Dallas, TX (US);
Mahesh J. Thakre, Dallas, TX (US);
Scott R. Summerfelt, Garland, TX (US);
Francis G. Celii, Dallas, TX (US);
Mahesh J. Thakre, Dallas, TX (US);
Scott R. Summerfelt, Garland, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (). Using the patterned hard mask layer (), the layers are etched to form an etched barrier layer (), and etched first metal layer (), and etched ferroelectric layer (), and etched second metal layers (). The etched layers form a ferroelectric memory capacitor () with sidewalls that form an angle with the plane of the upper surface of the dielectric layer () between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.