Methods of fabricating integrated circuit devices including self-aligned contacts with increased alignment margin

Abstract

An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions. A plurality of bit line structures are on the substrate, extending transverse to the word line structures and contacting the second conductive pads. Related methods of fabrication are also described.