Method for generating timing constraints of logic circuit

Abstract

In hierarchical design of a logic circuit by utilizing lower-level blocks of the logic circuit, data on the logic circuit with the hierarchical structure, library data holding primitive information on the logic circuit and timing constraints on the lower-level blocks are input at a data input step. Based on these input data, it is determined whether or not interface specifications of timing constraints on the lower-level blocks match each other at a matching determination step before a constraint converting step of converting the timing constraints on the lower-level blocks into a timing constraint on a higher-level block. Accordingly, it is possible to avoid generation of an excessively reduced or rigorous timing constraint on the higher-level block resulting from mismatching between interface specifications of timing constraints on the lower-level blocks.