The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2007

Filed:

Sep. 07, 2004
Applicants:

Yukinari Shibata, Sapporo, JP;

Nobuyuki Saito, Sapporo, JP;

Tomonaga Hasegawa, Sapporo, JP;

Takuya Ishida, Sapporo, JP;

Inventors:

Yukinari Shibata, Sapporo, JP;

Nobuyuki Saito, Sapporo, JP;

Tomonaga Hasegawa, Sapporo, JP;

Takuya Ishida, Sapporo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/26 (2006.01); G06F 1/32 (2006.01); H04B 1/10 (2006.01); H04B 1/04 (2006.01); H04B 1/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock signal CLK by driving a serial signal line, a PLL circuit which generates the clock signal CLK, and a power-down setting circuit which sets a power-down mode. In a first power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode, and the clock-transfer transmitter circuit is set to the power-down mode to stop a system clock signal of a target-side data transfer control device. In a second power-down mode, the OUT-transfer transmitter circuit is set to the power-down mode without setting the clock-transfer transmitter circuit to the power-down mode.


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