The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2007
Filed:
Apr. 03, 2003
Prasanna Sundararajan, Los Gatos, CA (US);
Carl H. Carmichael, San Jose, CA (US);
Scott P. Mcmillan, Santa Clara, CA (US);
Brandon J. Blodget, Santa Clara, CA (US);
Cameron D. Patterson, Longmont, CO (US);
Prasanna Sundararajan, Los Gatos, CA (US);
Carl H. Carmichael, San Jose, CA (US);
Scott P. McMillan, Santa Clara, CA (US);
Brandon J. Blodget, Santa Clara, CA (US);
Cameron D. Patterson, Longmont, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of 'care bits' (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the 'SEU Probability Impact' (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.