The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2007
Filed:
Mar. 08, 2005
Katsutoyo Misawa, Nukata-gun, JP;
Yasuyuki Ishikawa, Kariya, JP;
Akira Suzuki, Nukata-gun, JP;
Yoshinori Teshima, Toyota, JP;
Hideaki Ishihara, Okazaki, JP;
Toshiharu Muramatsu, Nishio, JP;
Katsutoyo Misawa, Nukata-gun, JP;
Yasuyuki Ishikawa, Kariya, JP;
Akira Suzuki, Nukata-gun, JP;
Yoshinori Teshima, Toyota, JP;
Hideaki Ishihara, Okazaki, JP;
Toshiharu Muramatsu, Nishio, JP;
DENSO CORPORATION, Kariya, JP;
Abstract
In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [VVtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [VVtn] when an excessive voltage of negative polarity is applied.