The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 24, 2007

Filed:

Dec. 29, 2004
Applicants:

Ruchir Saraswat, Vasundhara Ghaziabad, IN;

Balwant Singh, Greater Noida, IN;

Prashant Dubey, Ghaziabad, IN;

Inventors:

Ruchir Saraswat, Vasundhara Ghaziabad, IN;

Balwant Singh, Greater Noida, IN;

Prashant Dubey, Ghaziabad, IN;

Assignee:

STMicroelectronics PVT. Ltd., Uttar Pradesh, IN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 27/28 (2006.01); G01R 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.


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