The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2007
Filed:
Feb. 15, 2005
Rajeev Murgai, Santa Clara, CA (US);
Subodh M. Reddy, San Jose, CA (US);
Takashi Miyoshi, San Jose, CA (US);
Takeshi Horie, Palo Alto, CA (US);
Mehdi B. Tahoori, Brookline, MA (US);
Rajeev Murgai, Santa Clara, CA (US);
Subodh M. Reddy, San Jose, CA (US);
Takashi Miyoshi, San Jose, CA (US);
Takeshi Horie, Palo Alto, CA (US);
Mehdi B. Tahoori, Brookline, MA (US);
Fujitsu Limited, Kawasaki, JP;
Abstract
In one embodiment, a method for analyzing substrate noise includes applying a static timing analysis (STA) algorithm to a description of a digital circuit. Application of the STA algorithm generates timing information on one or more gates in the digital circuit. The method also includes applying a current waveform generation (CWG) algorithm to the description of the digital circuit, the timing information on one or more gates in the digital circuit, and a description of switching activity in the digital circuit. Application of the CWG algorithm generates a current waveform. The method also includes generating a reduced model (RM) of the digital circuit for simulation according to the description of the digital circuit, the current waveform, and a model of a package associated with the digital circuit. Simulation of the RM of the digital circuit generates an indication of noise in a substrate associated with the digital circuit.