The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2007

Filed:

Apr. 01, 2004
Applicants:

Tarek Eldin, San Jose, CA (US);

Zhi-min Ling, Cupertino, CA (US);

Feng Wang, San Jose, CA (US);

David M. Mahoney, Mountain View, CA (US);

Inventors:

Tarek Eldin, San Jose, CA (US);

Zhi-Min Ling, Cupertino, CA (US);

Feng Wang, San Jose, CA (US);

David M. Mahoney, Mountain View, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point ('PIP') in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.


Find Patent Forward Citations

Loading…