Integrated semiconductor memory with clock-synchronous access control

Abstract

An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such a way that when a noisy clock signal is applied to the integrated semiconductor memory device, the less sensitive input amplifier is used for generating an internal clock signal. If, by contrast, a lower-noise clock signal is applied to the integrated semiconductor memory device, the control circuit drives the controllable switch in such a way that the more sensitive input amplifier is used for generating the internal clock signal. The changeover of the controllable switch is effected after evaluation of a bit sequence applied to a further input terminal of the integrated semiconductor memory device.