Integrated semiconductor memory device including sense amplifiers

Abstract

An integrated semiconductor memory device includes a memory cell array with sense amplifiers that are combined in groups within the memory cell array. Each sense amplifier is associated with one data connection, the association varying on the basis of area within the memory cell array. When a memory cell is read, further adjacent memory cells besides the memory cell which is to be read are read, so that data are produced at all the data connections. To this end, the sense amplifiers in a group are activated together. To establish which sense amplifier within a group of sense amplifiers has a signaling connection to which data connection, individual sense amplifiers in a group can be deactivated specifically, which means that a data item which differs from an expected value appears at the data connection which is connected to the deactivated sense amplifier.