The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 17, 2007

Filed:

Mar. 07, 2006
Applicants:

Toan Thanh Nguyen, San Jose, CA (US);

Thungoc M. Tran, San Jose, CA (US);

Sergey Shumarayev, San Leandro, CA (US);

Inventors:

Toan Thanh Nguyen, San Jose, CA (US);

Thungoc M. Tran, San Jose, CA (US);

Sergey Shumarayev, San Leandro, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuit serializer circuitry is provided that converts parallel data to serial data on an integrated circuit. A two-phase global serializer master clock generator uses a four-phase internal clock to generate a two-phase global serializer master clock. The two-phase global serializer master clock is distributed globally on the integrated circuit using a distribution path. The integrated circuit has multiple serial communications channels each of which has an associated serializer. Each serializer contains circuitry that derives a number of clock signals from the two phases of the global serializer master clock. Each serializer uses the derived clocks in converting parallel data to serial data for transmission over its associated serial communications channel. The serializers each contain two smaller serializers that convert first and second sets of parallel data to first and second serial outputs. A 2:1 serializer in each serializer merges the first and second serial outputs.


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