The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7245177 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 17, 2007

Filed:

Jul. 27, 2004
Applicants:

Tetsuya Fujita, Tokyo, JP;

Motosugu Hamada, Palo Alto, CA (US);

Hiroyuki Hara, Tokyo, JP;

Inventors:

Tetsuya Fujita, Tokyo, JP;

Motosugu Hamada, Palo Alto, CA (US);

Hiroyuki Hara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 3/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.


Find Patent Forward Citations

Fujita, Tetsuya. (2007). Semiconductor integrated circuit and source voltage/substrate bias control circuit (U.S. Patent No. 7245177). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7245177

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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