The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2007
Filed:
Nov. 30, 2005
Jeffrey Alan Brigante, Colchester, VT (US);
Zhong-xiang He, Essex Junction, VT (US);
Barbara Ann Waterhouse, Richmond, VT (US);
Eric Jeffrey White, Charlotte, VT (US);
Jeffrey Alan Brigante, Colchester, VT (US);
Zhong-Xiang He, Essex Junction, VT (US);
Barbara Ann Waterhouse, Richmond, VT (US);
Eric Jeffrey White, Charlotte, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A structure and a method of forming the structure. The structure including: an integrated circuit chip having a set of wiring levels from a first wiring level to a last wiring level, each wiring level including one or more damascene, dual-damascene wires or damascene vias embedded in corresponding interlevel dielectric levels, a top surface of a last damascene or dual-damascene wire of the last wiring level substantially coplanar with a top surface of a corresponding last interlevel dielectric level; a capping layer in direct physical and electrical contact with a top surface of the last damascene or dual-damascene wire, the last damascene or dual-damascene wire comprising copper; a dielectric passivation layer formed on a top surface of the last interlevel dielectric level; and an aluminum pad in direct physical and electrical contact with the capping layer, a top surface of the aluminum pad not covered by the dielectric passivation layer.