The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 17, 2007
Filed:
Oct. 07, 2003
Michael A. Vyvoda, San Jose, CA (US);
Manish Bhatia, Sunnyvale, CA (US);
James M. Cleeves, Redwood City, CA (US);
N. Johan Knall, Sunnyvale, CA (US);
Michael A. Vyvoda, San Jose, CA (US);
Manish Bhatia, Sunnyvale, CA (US);
James M. Cleeves, Redwood City, CA (US);
N. Johan Knall, Sunnyvale, CA (US);
SanDisk Corporation, Milpitas, CA (US);
Abstract
A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.