The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Jul. 21, 2004
Thomas J. Mcintyre, Nokesville, VA (US);
Scott K. Arnold, Gainesville, VA (US);
Thomas J. McIntyre, Nokesville, VA (US);
Scott K. Arnold, Gainesville, VA (US);
BAE Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);
Abstract
A system is provided to aid in laying out circuits on a semiconductor wafer, in which a wafer map is automatically generated when entering chip sizes, arrangements and other enterable factors, with a goal to maximize yield probability. The subject system accommodates different chip types and arrangements within a wafer map and addresses edge exclusion, utilization of chiplets and accommodation of different centering techniques, including a variety of ways of measuring offsets, while outputting a display of replicated circuits on the wafer as well as chip count and density, utilizing a portable, tailorable, extendable PC-based program featuring an easy-to-use graphical interface. The software application provides a user with different graphical views customized for different process areas, such as lithography and dicing, with the application being useful for any semiconductor manufacturing facility, foundry or similar industry that needs to generate wafer maps automatically to maximize yield probability.