The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

Jun. 01, 2004
Applicants:

Tai an Ly, San Jose, CA (US);

Ka Kei Kwok, Milpitas, CA (US);

Vijaya Vardhan Gupta, San Jose, CA (US);

Ross Andrew Ander, Los Altos, CA (US);

Ping Fai Yeung, San Jose, CA (US);

Neil Patrick Hand, Menlo Park, CA (US);

Lawrence Curtis Widdoes, Jr., San Jose, CA (US);

Inventors:

Tai An Ly, San Jose, CA (US);

Ka Kei Kwok, Milpitas, CA (US);

Vijaya Vardhan Gupta, San Jose, CA (US);

Ross Andrew Ander, Los Altos, CA (US);

Ping Fai Yeung, San Jose, CA (US);

Neil Patrick Hand, Menlo Park, CA (US);

Lawrence Curtis Widdoes, Jr., San Jose, CA (US);

Assignee:

Other;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

During verification of a description of a circuit containing a pre-determined assertion, in order to detect incorrect behavior of the circuit that may be caused by metastability occurring in signals that cross clock domains ('CDC' signals) in the circuit, the description of the circuit is automatically transformed by addition of circuitry to inject the effects of metastability into the CDC signals. The transformed description containing the circuitry to inject metastability is verified in the normal manner. Certain embodiments analyze the transformed description using a model checking method to determine a stimulus sequence that will cause the pre-determined assertion to be violated. The transformed circuit is then simulated in some embodiments, using the stimulus sequence from model checking, and an incorrect behavior of the circuit due to metastability is displayed, for diagnosis by the circuit designer. The circuit designer may revise the circuit description and iterate as noted above.


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