The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

Aug. 18, 2005
Applicants:

Masafumi Yamazaki, Kawasaki, JP;

Takaaki Suzuki, Kawasaki, JP;

Toshikazu Nakamura, Kawasaki, JP;

Satoshi Eto, Kawasaki, JP;

Toshiya Miyo, Kawasaki, JP;

Ayako Sato, Kawasaki, JP;

Takayuki Yoneda, Kawasaki, JP;

Noriko Kawamura, Kawasaki, JP;

Inventors:

Masafumi Yamazaki, Kawasaki, JP;

Takaaki Suzuki, Kawasaki, JP;

Toshikazu Nakamura, Kawasaki, JP;

Satoshi Eto, Kawasaki, JP;

Toshiya Miyo, Kawasaki, JP;

Ayako Sato, Kawasaki, JP;

Takayuki Yoneda, Kawasaki, JP;

Noriko Kawamura, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An external terminal receives an external signal so as to access the first and second memory chips. The test starting terminal receives a test starting signal activated when the first or second memory chip is tested and inactivated when the first and second memory chips are normally operated. The access signal generator converts the external signal to a memory access signal of the first memory chip. The first selector selects the external signal, which is a test signal, during activation of the test starting signal, selects the memory access signal during the inactivation of the test starting signal. That is, during the test modes, the first memory chip can be directly accessed from the exterior. For this reason, the test program for testing the first memory chip alone can be diverted as the test program following an assembly of the semiconductor device.


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