The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

Feb. 04, 2004
Applicant:

Frank Boeh, Buchholz, DE;

Inventor:

Frank Boeh, Buchholz, DE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 35/00 (2006.01); G01R 23/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

In order to further develop a system () and a method for calibrating the clock frequency of at least one clock generator unit (), in particular oscillator unit, that is assigned to at least one transmitting/receiving module (), wherein—the transmitting/receiving module () communicates with at least one microcontroller unit () over at least one data line () and—the clock generator unit () is assigned at least one calibration unit (), in such a manner that with significantly reduced system costs the clock frequency of the clock generator unit () can be calibrated with very high accuracy, it is proposed that—in order to calibrate the clock frequency of the clock generator unit () at least one calibration unit () is assigned to the clock generator unit), —the calibration unit () can be set in binary terms by means of at least one command signal (COM) via the data line (), —the clock generator unit () is assigned at least one binary counter () that is clocked by the clock generator unit (), in particular by the output frequency (fout) of the clock generator unit () and—within the transmitting/receiving module () there is at least one control logic mechanism () which is connected (STA, OFL or SET) to the calibration unit () or to the binary counter (), which control logic mechanism, following reception of the command signal (COM), resets the binary counter (), starts it (STA) and awaits the expiry or overflow (OFL) of the binary counter ().


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