The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Jun. 08, 2005
Christopher A. Nicolls, Rehoboth, MA (US);
Roger D. Mayer, Rehoboth, MA (US);
Christopher A. Nicolls, Rehoboth, MA (US);
Roger D. Mayer, Rehoboth, MA (US);
Sensata Technologies, Inc., Attleboro, MA (US);
Abstract
A tester for an arc fault circuit interrupter that can selectively simulate and apply electrical arc faults and nuisance loads to at least one device under test (DUT). The tester includes a power supply, a test controller, and test circuitry coupleable to a DUT. AC power input is provided to the DUT and the power supply, which regulates the AC power input to a DC level for powering the test controller. The test circuitry full wave rectifies AC current returning from the DUT, and the test controller controls a switch in the test circuitry. When the switch is on, the AC current flows through the DUT, the full wave rectifier, the load, and the switch to ground. To simulate an arcing condition, the test controller turns the switch on and off at random intervals. To simulate a nuisance load condition, the test controller turns the switch on and off at periodic intervals. In this way, proper operation of the DUT can be verified under both arcing and nuisance load conditions.