The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

May. 23, 2006
Applicants:

Tetsunori Otaguro, Tokyo, JP;

Seiji Matsuda, Tokyo, JP;

Inventors:

Tetsunori Otaguro, Tokyo, JP;

Seiji Matsuda, Tokyo, JP;

Assignee:

Hirata Corporation, Shinagawa-Ku, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a substrate aligning system which prevents particles or the like from attaching to a substrate such as a wafer used in the semiconductor manufacturing process, and adjusts the orientation of the substrate accurately within a short period of time. According to a substrate aligning system (A) as a preferred embodiment of the present invention, a plurality of rollers () push the peripheral portion of a wafer (W) from different directions to align the center of the wafer. While the center of the wafer is kept aligned by the rollers (), the contacting portion () of a contacting member () contacts a chip (Wa) of the wafer (W). The contacting member () is then moved arcuately to rotate the wafer (W), thus adjusting the orientation of the wafer.


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