The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 10, 2007

Filed:

Oct. 29, 2004
Applicants:

Richard Lee Donze, Rochester, MN (US);

Karl Robert Erickson, Rochester, MN (US);

William Paul Hovis, Rochester, MN (US);

Terrance Wayne Kueper, Rochester, MN (US);

John Edward Sheets, Ii, Zumbrota, MN (US);

Jon Robert Tetzloff, Rochester, MN (US);

Inventors:

Richard Lee Donze, Rochester, MN (US);

Karl Robert Erickson, Rochester, MN (US);

William Paul Hovis, Rochester, MN (US);

Terrance Wayne Kueper, Rochester, MN (US);

John Edward Sheets, II, Zumbrota, MN (US);

Jon Robert Tetzloff, Rochester, MN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.


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