Simulation method for semiconductor circuit device and simulator for semiconductor circuit device

Abstract

A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias fate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When the negative bias voltage is terminated by applying a bias free voltage, the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm 'log(t)' is obtained for an application time 't' of the gate voltage, a deterioration amount ΔP(t)=C+B·log(t) is calculated by using constants Cand Bdepending on the negative bias voltage, a recovery amount ΔP(t)=C+B·log(t) is calculated by using constants Cand Bdepending on the bias free voltage, and the deterioration amount (ΔP), the recovery amount (ΔP) and a basic deterioration amount (X) are summed up.