Circuit for bit skew suppression in high speed multichannel data transmission

Abstract

A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge. A plurality of n samplers to generate a first set of N/2 sampled signals on the positive phases and a second set of N/2 sampled signals on the negative phases. A corresponding plurality of n phase selectors to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase. A control logic block configured to receive a corresponding plurality of n first control signals. A data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.