The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Apr. 02, 2004
Tan BA Tran, Round Rock, TX (US);
Gerard Richard Williams, Sunset Valley, TX (US);
David Terrence Matheny, Austin, TX (US);
David Walter Flynn, Cambridge, GB;
Tan Ba Tran, Round Rock, TX (US);
Gerard Richard Williams, Sunset Valley, TX (US);
David Terrence Matheny, Austin, TX (US);
David Walter Flynn, Cambridge, GB;
Arm Limited, Cambridge, GB;
Abstract
A data processor corecomprising: a memory access interface portionoperable to perform data transfer operations between an external data source and at least one memoryassociated with said data processor core; a data processing portionoperable to perform data processing operations; a read/write portoperable to transfer data from said processor core to at least two busesA,B said at least two buses being operable to provide data communication between said processor coreand said at least one memory, said at least one memorycomprising at least two portionsA,B, each of said at least two busesA,B being operable to provide data access to respective ones of said at least two portionsA,B; arbitration logicassociated with said read/write port; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.