Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same

Abstract

A SONET demapper includes three desynchronizers, each of which includes a RAM-based, shared digital phase locked loop, shared elastic storage, and twenty-eight divide-by 33/34/44/45 counters. Unlike a conventional desynchronizer which uses separate FIFOs for each of the twenty-eight T1/E1 channels, the elastic storage for each channel is an addressed portion of a shared block of RAM. Each desynchronizer generates a clock for each of the twenty-eight T1/E1 channels based on a FIFO depth count for each channel which is derived from a read pointer, an 'effective write pointer', and the divide-by clock for the channel. Each desynchronizer can desynchronize both T1/E1 signals as well as a combination of these signals. In addition, the invention combines the leak FIFO and desynchronizer FIFO into a single FIFO with an effective write pointer. This eliminates the need to maintain separate counters and pointers for separate FIFOs.