The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2007

Filed:

Jan. 21, 2005
Applicants:

Shun-lih Tu, Taipei, TW;

Chih-hung Chuang, Hsinchu, TW;

Huai-ku Chung, Hsinchu, TW;

Chia-feng Yang, Yungho, TW;

Cheng-wei Yang, Chilung, TW;

Tsu-an Han, Kaohsiung Hsien, TW;

Hung-tung Wang, Hsinchu, TW;

Chien-chen Hung, Hsinchu, TW;

Inventors:

Shun-Lih Tu, Taipei, TW;

Chih-Hung Chuang, Hsinchu, TW;

Huai-Ku Chung, Hsinchu, TW;

Chia-Feng Yang, Yungho, TW;

Cheng-Wei Yang, Chilung, TW;

Tsu-An Han, Kaohsiung Hsien, TW;

Hung-Tung Wang, Hsinchu, TW;

Chien-Chen Hung, Hsinchu, TW;

Assignee:

Opto Tech Corporation, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B41J 2/45 (2006.01); H01L 27/00 (2006.01); H01L 21/70 (2006.01); H01L 21/77 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to the method, a trench structure is formed in a substrate. LED arrays and driver ICs are located in the corresponding trenches. An insulating layer is formed over the substrate, the LED arrays and the driver ICs. A photolithography process forms an electrical connection structure between the LED arrays and the driver ICs. Then, a die-cutting process cuts out individual units. These units are fixed in a PCB and an electrical connection structure is formed between these units and input/output pins on the PCB.


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