The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Sep. 25, 2003
Ji Ung Lee, Niskayuna, NY (US);
Reed Roeder Corderman, Niskayuna, NY (US);
William Hullinger Huber, Scotia, NY (US);
Ji Ung Lee, Niskayuna, NY (US);
Reed Roeder Corderman, Niskayuna, NY (US);
William Hullinger Huber, Scotia, NY (US);
General Electric Company, Niskayuna, NY (US);
Abstract
A self-aligned gated field emission device and an associated method of fabrication are described. The device includes a substrate and a porous layer disposed adjacent to the surface of the substrate, wherein the porous layer defines a plurality of substantially cylindrical channels, each of the plurality of substantially cylindrical channels aligned substantially parallel to one another and substantially perpendicular to the surface of the substrate. The device also includes a plurality of substantially rod-shaped structures disposed within at least a portion of the plurality of substantially cylindrical channels defined by the porous layer and adjacent to the surface of the substrate, wherein a portion of each of the plurality of substantially rod-shaped structures protrudes above the surface of the porous layer. The device further includes a gate dielectric layer disposed on the surface of the porous layer, wherein the gate dielectric layer is disposed between the plurality of substantially rod-shaped structures. The device still further includes a conductive layer selectively disposed on the surface of the gate dielectric layer, wherein the conductive layer is selectively disposed between the plurality of substantially rod-shaped structures.