The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 03, 2007

Filed:

Jul. 07, 2005
Applicants:

Kouki Ogawa, Aichi, JP;

Eiji Kodera, Gifu, JP;

Inventors:

Kouki Ogawa, Aichi, JP;

Eiji Kodera, Gifu, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A capacitor-built-in-type printed wiring substrate which can reliably eliminate noise and attain extremely low resistance and low inductance in connections between an IC chip and the capacitor, and a printed wiring substrate and capacitor for use in the same. A capacitor-built-in-type printed wiring substrateon which an IC chip is mounted includes a capacitor-built-in-type printed wiring substrateand an IC chipmounted on the capacitor-built-in-type printed wiring substrate. A printed wiring substrateincludes a number of connection-to-IC substrate bumpsand a closed-bottomed capacitor accommodation cavityformed therein. A capacitoris disposed in the cavityand includes a pair of electrode groupsE andF and a number of connection-to-IC capacitor bumpsconnected to either one of the paired electrode groupsE andF. The connection-to-IC capacitor bumpsare flip-chip-bonded to corresponding connection-to-capacitor bumpson the IC chip. The connection-to-IC substrate bumpsare flip-chip-bonded to corresponding connection-to-substrate bumpson the IC chip


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